Today's general-purpose dynamic superscalar processors use large on-chip regular structures, such as the register file and caches, in order to exploit the available instruction-level parallelism and improve performance. These structures are often designed in order to maximize the performance of the average application. There is, however, a trade-off between the size of these structures and their speed and power consumption. The best design may differ on a per application and even a per phase basis.
In this talk, I will present some of the techniques we have developed to improve the utilization of cycle time critical structures such as the register file, as well as to leverage technology trends in order to effect speed and power trade-offs dynamically. First, I will present a novel microarchitecture designed to overcome the limitations of a register file size dictated by cycle time constraints. Next, I will describe a tunable cache and TLB (translation lookaside buffer) hierarchy that leverages repeater insertion to provide dynamic low-cost configurability. This hierarchy is controlled by a novel configuration management algorithm that trades the sizes of the cache and TLB for their speed and power consumption on a per application phase basis. Finally, I will present a glimpse of our efforts to apply these techniques globally across the chip for dynamic scaling of voltage, frequency, and size for reduced energy consumption.
About Sandhya Dwarkadas
Sandhya Dwarkadas is an Associate Professor of Computer Science and of Electrical and Computer Engineering at the University of Rochester. She received her Bachelor's degree from Indian Institute of Technology, Madras, India, in 1986 and her Ph.D. in Electrical and Computer Engineering from Rice University in 1993, where she continued as a research scientist in the Computer Science department until 1996. Her research interests are in parallel and distributed systems, computer architecture, compiler/architecture/run-time interaction, and performance evaluation. Dr. Dwarkadas has been the recipient of a NSF CISE Experimental Science Postdoctoral Fellowship (1993-1995), and an NSF CAREER Award for junior faculty (1997-2000).
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