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Department of Computer Science
Rice University

Processor ARCHITECTURES FOR 100 Nanometers and Beyond

Stephen W. Keckler
Computer Architecture and Technology Laboratory
The University of Texas at Austin

Abstract

Conventional microarchitectures face two challenges to continued performance scaling. First, the rate of clock speed improvements will soon slow considerably, putting pressure on concurrency to bridge the performance gap. Second, today's superscalar architectures are facing diminishing returns in instruction level parallelism, particularly with increased on-chip interconnect delays looming in the immediate future.

In this talk, Keckler will describe a microarchitecture that is designed to exploit both higher clock rates and higher ILP than current designs. This Grid Processor Architecture (GPA) consists of an array of ALUs connected via a thin network of direct communication paths. The architecture exposes communication latencies to the instruction scheduler for optimization, which then attempts to minimize the physical distance among instructions along the critical path. The GPA permits an implementation with a large effective instruction window, eliminates large shared structures from the execution critical paths in the steady state, and allows for faster clock speeds in a given technology than conventional designs. Current simulations demonstrate that even taking into account realistic communication delays, the instructions per clock (IPC) of the GPA exceeds that of idealized conventional microarchitectures.

The research described in this talk is a collaboration with Prof. Doug Burger and the students in the CART group at UT-Austin.

About Stephen W. Keckler

Stephen W. Keckler is an Assistant Professor of both Computer Sciences and Electrical and Computer Engineering at the University of Texas at Austin, where he co-directs the Computer Architecture and Technology (CART) Laboratory. His research interests include developing computer system architectures that scale with technology and can adapt to application and environmental demands. Dr. Keckler earned his BS in Electrical Engineering from Stanford University in 1990, and his MS and Ph.D. in Computer Science from the Massachusetts Institute of Technology in 1992 and 1998.

Monday, October 29 at 4 p.m. in DH 1070
A reception will precede the talk at 3:30 in DH 3092.

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