Today's media processing applications demand very high arithmetic rates, and compelling applications of the future promise to further increase this demand. Fortunately, these applications have large amounts of inherent parallelism. The challenge in media processor design, therefore, is to efficiently support the large number of arithmetic units needed to exploit this parallelism. In this talk, I will discuss the Imagine Stream Processor and the architectural motivation for its underlying stream architecture which is designed for high-performance media processing.

The storage structures of the stream architecture address modern VLSI constraints while providing the bandwidth necessary to support large numbers of arithmetic units. By partitioning the register file structure, its cost in terms of area, delay, and power can be greatly reduced. The partitioned stream register file organization utilizes a bandwidth hierarchy to amplify the data bandwidth of the memory system for the arithmetic units. The memory bandwidth at the base of this hierarchy must be utilized efficiently in order to meet the demands of the numerous arithmetic units. This can be accomplished by scheduling memory accesses to exploit the available parallelism in modern DRAMs. The Imagine Stream Processor incorporates these concepts, yielding a high-performance processor capable of sustaining in excess of 10GOPS on media processing applications.