Chapter 3

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Basic pipelining steps: Instruction Fetch, Instruction Decode, Execute, Memory, WriteBack. However, modern day architectures have upto around 20 pipeline stages.

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Three types of hazards in a pipeline:

1. Structural: When there is resource conflict. E.g. two stages want to write to the register file in the same clock cycle.

2. Data: Data is not ready for the next instruction since the output of the previous instruction is made available only at the end of Writeback stage whereas the data for the next instruction is required in the Instruction Decode stage. There are various type, RAW - the read happens before the write, WAW - the second write happens before the first write, and WAR - the write happens before the read.

3. Control: If the PC is not incremented by 4 due to a branch instruction then if we blindly allow the PC to increment by 4 we will execute wrong code.

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Superpipelining: Suppose there are 5 stages in a pipeline and one of the stages takes 10 s whereas the other stages take 2 seconds each. Then the architecture can support at most 1 instruction every 10 seconds. So in order to do improve this the 10 s stage is divided into smaller pipeline stages, each of say latency 2 s. Now there are 4 + 5 = 9 pipeline stages but the architecture can now support 1 instruction every 2 seconds. This concept is called superpipeling.

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It seems that WAW exceptions should never take place because which compiler would generate code that would write the later value before the earlier write. However, this situation can arise while trying to handle branches efficiently. For example, while the branch is evaluated if we run some code which is after the branch body (and hence guaranteed to run anyway) that code might write to some memory location which actually should have been written to by an an instruction which is inside the branch body. If the branch were not to be taken then everything would be correct but if the branch is taken then there can be a WAW hazard.