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[ Proposal ] [ Final Report ] [ Final Presentation ]
It is trivial to write malicious code that hogs up a particular resource, for example, memory, disk, etc. Such malicious code can be written by intent (in order to degrade the performance of the system considerably) or by mistake (for example, memory leaks). As an effect of running such a code the other applications running on the same machine suffer and their performance degrade considerably. Such kind of resource overbooking is a prevalent problem. In this project we present two approaches to reduce the problem of resource overbooking. We consider the specific case of the resource being main memory. However, our approaches are general enough to be applied to other resource such as disk, CPU, network bandwidth, etc.
[ Final Report ] [ Final Presentation ]
This project aims to compare two different implementations of a cache coherence protocol namely, the MESI coherence protocol. The first is a directory-based implementation of the MESI protocol whereas the second is a snoopy implementation. The snoop implementation is different in the sense that it uses the shared snoopy bus for address only whereas the data is transferred point-to-point. Our results show that the snoopy implementation has some definite advantages over the directory-based implementation. However, the manifestation of these advantages in the form of speedup depends a lot upon the application being run on the processor.
The project includes the simulation of Flow State extensions to to DSR (Dynamic Source Routing), a routing protocol for mobile ad hoc networks. Flow State routing deceases the routing overhead that is involved with each packet in a typical source routing protocol such as DSR.
[ Final Report ] [ Final Presentation ]
If the trace cache size is not large enough to contain all of the basic blocks of the running application, a judicious hit and replacement logic becomes very important. This project proposes a weight-based technique to select the victim line in the trace cache for the replacement logic. It also presents judicious line-fill buffer logic which is found to decrease the redundancy in the trace cache. We did the performance study by simulating these techniques on SimpleScalar. For SimpleScalar test benchmark applications, a trace cache with the proposed replacement and line-fill buffer logic was found to provide 1-5% better IPC than a trace cache with a Least Recently Used replacement logic.
[ Final Report ]
We propose a Coordinated Asymmetric Multi Process Event Driven AMPED architecture for a web server executing on a Symmetric Multiprocessor (SMP) system. For a k - processor SMP system we execute k copies of an AMPED process which coordinate among themselves to optimise the utilisation of the cache across the k processes. We compared the performance of the proposed model against a Multi Process (MP) architecture and found that it performed 50% better on an average. However, we found that there is no improvement by increasing the number of main processes in any of the architectures considered. Instead the AMPED implementation without any modifications was performing the best. For our analysis we used the Flash version of MP and made changes to the Flash implementation of AMPED to get an implementation of the Co-AMPED architecture.
[ Final Report ]
Existing MAC protocols for wireless LAN systems assume the availability of only one frequency for all the nodes. Our protocol explores the possibility of higher throughput under the existence of multiple orthogonal frequency channels. We simulated the proposed protocol on ns-2 simulator. We showed that our simple protocol is capable of much better performance compared to single frequency channel for all nodes.
[ Project Webpage ] Webpage made unreadable on instructor's request.
In this project we proposed a few heuristics decrease the running time for the Minimum Spanning Tree (MST) algorithm.