I'm a Computer Science Ph.D. graduate student at Rice University. I joined the program in 2004 after completing a BS in Computer Science at Michigan Tech University. My advisor is Dr. Keith Cooper.

I completed my MS thesis in May 2007: "Tuning an Adaptive Compilation Search Space with Loop Unrolling.". My research interests mainly focus on compilers and program optimization, but the Adaptive Compilation work for my MS thesis introduced me into the exciting world of artificial intelligence. For my Ph.D., I am exploring aggressive runtime reoptimization techniques. I believe that the current trend in multi-core architectures introduces a big opportunity for observing and improving program performance at runtime. Multi-core architectures appear to be here to stay -- evidence suggests that the number of cores will continue to grow rapidly. Unfortunately, the most common programming paradigms do not enable programmers to easily and efficiently express parallelism. The complexity of current superscalar processors already makes it difficult for programmers to achieve high processor utilization, but the increase in cores will severely aggravate this problem. Thus, we face a future where computer programs will use smaller and smaller fractions of the available processor resources. By allocating a small number of unused cores for program observation and reoptimization, we can improve program performance without incurring intolerable overheads. This approach allows more detailed performance analysis and more aggressive optimization than used by previous runtime techniques, because the multi-core parallelism allows most of the overhead to be moved off of the critical path of the target application.

I spent three months in the summer of 2007 working as an intern at Qualcomm. I worked on the compiler for Qualcomm's next-generation DSP processor.

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Fall 2004: