COMP 522 Multi-core Computing Fall 2013 Resources

The Future of Chip Design

• The Chip Design Game at the End of Moore's Law. Robert Colwell. Hot Chips 25 Keynote. Hot Chips A Symposium on High Performance Chips. August, 2013.

The Future of Chip Design

• CHESS: Find and Reproduce Heisenbugs in Concurrent Programs
  • Testing Finding and Reproducing Heisenbugs in Concurrent Programs. M. Musuvathi, S. Qadeer, T. Ball, G. Basler, P. A. Nainar, I. Neamtiu. In Operating System Design and Implementation (OSDI), 2008.
  • Verification: Effective Program Verification for Relaxed Memory Models. S. Burchkardt and M. Musuvathi. In 20th International Conference on Computer Aided Verification (CAV), 2008.
• The Multicore Challenge. David Patterson, Computing Community Consortium Blog, August 26, 2008.
• Tera-scale computing. Intel Technology Journal, Volume 11, Issue 3, August, 2007.
• Transactional Memory. James R. Larus and Ravi Rajwar. Morgan and Claypool. 2006. ISBN 9781598291247.
• Improving the Performance of Direct-Mapped Caches by the Additional of a Small Fully-Associative Cache and Prefetch Buffers. Norman Jouppi. In Proceedings of the 17th Annual international Symposium on Computer Architecture (ISCA), Seattle, Washington, May 28-31, 1990. ACM Press, New York, NY, 364-373. (Winner of the ACM/IEEE Influential paper award, 2005.)
• BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging, Satish Narayanasamy, Gilles Pokam, and Brad Calder, in Proceedings of the 32nd Annual International Symposium on Computer Architecture Madison, Wisconsin USA June 4-8, 2005. Published in SIGARCH Computer Architecture News 33, 2 (May. 2005), 284-295.

Compiler Optimization of Transactions

• Optimizing memory transactions, Tim Harris, Martin Plesko, Avraham Shinnar, and David Tarditi, in Proceedings of the ACM Conference on Programming Language Design and Implementation, June 2006. Published in SIGPLAN Notices 41, 6 (Jun. 2006), 14-25.

Concurrent Data Structures

• A methodology for implementing highly concurrent data structures, Maurice Herlihy, in Proceedings of the Second ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (Seattle, Washington, United States, March 14 - 16, 1990). PPOPP '90. ACM Press, New York, NY, 197-206.

More Debugging

• Learning from mistakes: a comprehensive study on real world concurrency bug characteristics, S. Lu, S. Park, E. Seo, and Y. Zhou, in SIGARCH Comput. Archit. News 36, 1 (Mar. 2008), 329-339.
• Eraser: a dynamic data race detector for multithreaded programs, Stefan Savage, Michael Burrows, Greg Nelson, Patrick Sobalvarro, and Tom Anderson, in ACM Trans. Comput. Syst. 15, 4 (Nov. 1997), 391-411. In Proceedings of the 16th ACM symposium on Operating systems principles. Saint Malo, France, 27-37, 1997.
• SharC: checking data sharing strategies for multithreaded C. Z. Anderson, D. Gay, R. Ennals, and E. Brewer, in Proceedings of the 2008 ACM SIGPLAN Conference on Programming Language Design and Implementation (Tucson, AZ, USA, June 07 - 13, 2008). PLDI '08. ACM, New York, NY, 149-158.
• Recording shared memory dependencies using strata, Narayanasamy, S., Pereira, C., and Calder, B. 2006. In Proceedings of the 12th international Conference on Architectural Support For Programming Languages and Operating Systems (San Jose, California, USA, October 21 - 25, 2006). ASPLOS-XII. ACM Press, New York, NY, 229-240.

Power

• Managing energy-performance tradeoffs for multithreaded applications on multiprocessor architectures. Soyeon Park, Weihang Jiang, Yuanyuan Zhou, and Sarita Adve. SIGMETRICS Perform. Eval. Rev. 35, 1 (Jun. 2007), 169-180.
• An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, and Margert Martonosi. In Proceedings of the 39th Annual IEEE/ACM international Symposium on Microarchitecture (December 09 - 13, 2006). International Symposium on Microarchitecture. IEEE Computer Society, Washington, DC, 347-358.

Thread-level Speculation

• Speculative thread decomposition through empirical optimization. Troy A. Johnson, Rudolf Eigenmann, T. N. Vijaykumar.In Proceedings of the 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (San Jose, California, USA, March 14 - 17, 2007). PPoPP '07. ACM Press, New York, NY, 205-214.
• Tight analysis of the performance potential of thread speculation using SPEC CPU 2006. Arun Kejariwal, Xinmin Tian, Milind Girkar, Wei Li, Sergey Kozhukhov, Utpal Banerjee, Alexandru Nicolau, Alexander V. Veidenbaum, Constantine D. Polychronopoulos.In Proceedings of the 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (San Jose, California, USA, March 14 - 17, 2007). PPoPP '07. ACM Press, New York, NY, 215-225.

Implementing Memory Models

• Conditional Memory Ordering, Cristoph von Praun, Harold Cain, Jong-Deok Choi, and Kyung Dong Ryu, in Proceedings of the 33rd International Symposium on Computer Architecture, June 17-21, 2006. Published in SIGARCH Computer Architecture News 34, 2 (May. 2006).
• Memory Model = Instruction Reordering + Store Atomicity, Arvind and Jan-Willem Maessen, in Proceedings of the 33rd international Symposium on Computer Architecture (June 17 - 21, 2006). International Conference on Computer Architecture. IEEE Computer Society, Washington, DC, 29-40.

Hardware Support for Fast Synchronization

• Techniques for reducing overheads of shared-memory multiprocessing, Alain Kägi, Nagi Aboulenein, Doug Burger, and James Goodman, in Proceedings of the 9th international Conference on Supercomputing (Barcelona, Spain, July 03 - 07, 1995). ICS '95. ACM Press, New York, NY, 11-20.
• Speculative synchronization: applying thread-level speculation to explicitly parallel applications, Jose Martínez and Josep Torrellas, in Proceedings of the 10th international Conference on Architectural Support For Programming Languages and Operating Systems (San Jose, California, October 05 - 09, 2002). ASPLOS-X. ACM Press, New York, NY, 18-29.

Hybrid Transactional Memory

• Hybrid Transactional Memory, M. Moir, Unpublished manuscript, July 2005.
• LogTM: Log-based Transactional Memory K. E. Moore, J. Bobba, M. J. Moravan, M. D. Hill, and D. A. Wood, International Symposium on High Performance Computer Architecture (HPCA), February 2006.

Optimizing for Multi-core Platforms

• Lattice Boltzmann Simulation Optimization on Leading Multicore Platforms, S. Williams, J. Carter, L. Oliker, J. Shalf, K. Yelick, in International Parallel & Distributed Processing Symposium (IPDPS), 2008.
• Optimization of Sparse Matrix-Vector Multiplication on Emerging Multicore Platforms, Samuel W. Williams, Leonid Oliker, Richard Vuduc, Katherine Yelick, James Demmel, John Shalf Supercomputing (SC), 2007.

Automatic Derivation of Concurrent Data Structures

• Deriving linearizable fine-grained concurrent objects, M. Vechev and E. Yahav, in Proceedings of the 2008 ACM SIGPLAN Conference on Programming Language Design and Implementation (Tucson, AZ, USA, June 07 - 13, 2008). PLDI '08. ACM, New York, NY, 125-135.
• Sketching concurrent data structures. A. Solar-Lezama, C.G. Jones, and R. Bodik, In Proceedings of the 2008 ACM SIGPLAN Conference on Programming Language Design and Implementation (Tucson, AZ, USA, June 07 - 13, 2008). PLDI '08. ACM, New York, NY, 136-148.

Hardware support for Transactional Memory

• Transactional Memory Coherence and Consistency , L. Hammond, V. Wong, M. Chen, B. Hertzberg, B. Carlstrom, M. Prabhu, H. Wijaya, C. Kozyrakis, and K. Olukotun, Proceedings of the 31st Annual International Symposium on Computer Architecture, München, Germany, June 2004.