COMP 635: Seminar on Heterogeneous Processors


Fall 2008 schedule:

  1. •Mondays, 3:30pm - 4:30pm, Keck 101 (first class is on August 25th)

  2. •30 minutes reserved after each lecture for discussion (optional)


Instructor: Vivek Sarkar            Assistant: Bob Garcia, DH 3137, x4476, rxg@rice.edu


Course Summary:


The computer industry is at a major inflection point in its hardware roadmap due to the end of a decades-long trend of exponentially increasing clock frequencies.  It is widely agreed that spatial parallelism in the form of multiple cores and multiple processing units must be exploited to compensate for this lack of frequency scaling.  Unlike previous generations of hardware evolution, this shift will have a profound impact on software.


In this seminar, we will focus on emerging trends in tightly coupled heterogeneous processors, which have the potential to deliver order-of-magnitude improvements in performance and power relative to homogeneous multicore processors but also pose the greatest challenges for software enablement.  We will study heterogeneous processor designs being developed in industry and academia that are aimed at integrating conventional processors with  specialized processors that span the range of FPGAs, stream processors, and processing units with local memories including GPGPUs.  We will critique current programming models and runtime interfaces for these designs, review past experiences with heterogeneous processors in the literature, and discuss the research challenges involved in implementing a simple, scalable and portable programming model and runtime for future generations of multicore heterogeneous processors.


The seminar will have a participatory format.  We will meet weekly to study different heterogeneous processor and their software environments.  In many cases, real hardware is available for experimentation as well.


Course Outline:

  1. •Introduction to Heterogeneous Processors and their Programming Models

  2. •Nvidia GPU and CUDA programming environment

  3. •Cell Processor and Cell SDK

  4. •Larrabee Many-Core x86 Architecture and Programming Model

  5. •Clearspeed Accelerator and SDK

  6. •Imagine Stream Processor

  7. •FPGA Accelerators

  8. •Accelerator Library Frameworks

  9. •Programming Model and Runtime Desiderata for future Heterogeneous Processors