Optimizing VHDL Intermediate Representations

Rice University, DARPA/ITO, and USAFRL

Keith D. Cooper, John Bennett, and Linda Torczon

USAFRL Contract F33615-97-C-1125

Project Overview

Today, many digital devices are derived from software specifications. Increasingly, people write "code" to build "hardware". The tools used to translate specifications into circuitry are analogous to traditional compilers. The goal of this project is to bring tools and techniques developed for use in traditional optimizing compilers to bear on the problem of improving the quality of translation from software specifications into to hardware. (We recognize that the target hardware can take many forms, ranging from programmable devices like FPGAs through custom chips. As in all translation problems, significant changes in the architecture of the target device can change the qualities that are desirable in the translation.)

This project was funded from the fall of 1997 to the fall of 2000.

Artifacts

The project produced a number of artifacts that are available via ftp.

Project Final Report
Project Final Review (Slides from the presentation)
An EDIF 2.0.0 parser & pretty-printer built on the "flex" and "yacc" tools. This is the second release of the parser.

We anticipate placing additional software and a technical report on Value Numbering VHDL-derived circuits on this site during the Spring of 2001.