Rice University

Professor
Computer Science
Electrical and Computer Engineering

Rice Computer Architecture
Rice University

Contact

E-Mail: Scott.Rixner@rice.edu
Office: Duncan Hall 3032
Address: Rice University
Dept. of Computer Science, MS 132
6100 Main St.
Houston, TX 77005
Phone: 713-348-6353
Office Hours: Spring 2016: by appointment

Teaching

  • Computer Science Undergraduate Lunch Talk Series
  • ENGI 128 - Introduction to Engineering Systems (Fall 2010)
  • COMP 140 - Computational Thinking (Fall 2015)
  • COMP 160 - Introduction to Computer Gaming (Fall 2012)
  • COMP 182 - Algorithmic Thinking (Spring 2013)
  • COMP 215 - Introduction to Program Design (Fall 2011)
  • COMP 310 - Advanced Object-Oriented Programming (Fall 2010)
  • COMP 321 - Introduction to Computer Systems (Spring 2015)
  • COMP/ELEC 519 - Network Systems Architecture (Spring 2008)
  • COMP/ELEC 525 - Advanced Microprocessor Architecture (Spring 2007)
  • COMP 528 - System-level Virtualization (Spring 2016)
  • ELEC 693 - Advanced Topics - Computer Systems (Fall 2009)
  • ELEC 696 - Computer Architecture Seminar (Spring 2011)

Massive Open Online Courses

Courses

Tools

I have developed CodeSkulptor, a browser-based Python environment for devloping interactive applications. We are using this environment in our Coursera course and at Rice and hope to deploy it more widely for education.

Media

Research

Scott Rixner is a Professor in the Computer Science & Electrical and Computer Engineering departments at Rice University. He leads the Rice Computer Architecture Group, and his research interests include media, network, and communications processing; the interaction between operating systems and computer architectures; and memory system architecture. During his doctoral studies, Rixner was the principal architect of the Imagine Stream Processor. His current research focuses on embedded systems, network server architecture, network virtualization, and memory system architecture.

Some of his recent publications include:

  • Surviving Peripheral Failures in Embedded Systems (USENIX ATC 2015)
  • Predictive Parallelization: Taming Tail Latencies in Web Search (SIGIR 2014)
  • Medusa: Managing Concurrency and Communication in Embedded Systems (USENIX ATC 2014)
  • An Environment for Learning Interactive Programming (SIGCSE 2014)
  • Hyper-switch: A Scalable Software Virtal Switching Architecture (USENIX ATC 2013)
  • Adaptive Parallelism for Web Search (EUROSYS 2013)
  • Design and Implementation of an Embedded Python Run-Time System (USENIX ATC 2012)
  • SpecTLB: A Mechanism for Speculative Address Translation (ISCA 2011)
  • Translation Caching: Skip, Don't Walk (the Page Table) (ISCA 2010)

You can find further information on his research and publications on the Rice Computer Architecture Group page. You can also find his publications on Google Scholar.

Patents

Scott Rixner has several pending and issued patents, including:
  • US Patent #8,984,184. Thomas W. Barr and Scott Rixner. System and method for managing input/output data of peripheral devices. Issued March 17, 2015.
  • US Patent #8,761,152. Scott Rixner, Alan L. Cox, Michael Foss, and Jeffrey Shafer. Method and system for scalable ethernet. Issued June 24, 2014.
  • US Patent #7,979,666. Scott Rixner, Kartik Mohanram and Mihir R. Choudhury. System and method for context-independent codes for off-chip interconnects. Issued July 12, 2011.
  • US Patent #7,818,539. Scott Rixner, John D. Owens, and Ujval Kapasi, and William J. Dally. System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values. Issued October 19, 2010.
  • US Patent #7,707,384. William J. Dally and Scott Rixner. System and method for re-ordering memory references for access to memory. Issued April 27, 2010.
  • US Patent #6,192,384. William J. Dally, Scott Rixner, J.P. Grossman, and Chris Buehler. System and method for performing compound vector operations. Issued February 20, 2001.
  • US Patent #6,016,531. Scott Rixner and C. Ross Ogilvie. Apparatus for performing real time caching utilizing an execution quantization timer and an interrupt controller. Issued January 18, 2000.

Curriculum

Education

  • Ph.D. in Electrical Engineering, MIT, 2001.
  • M.Eng. in Electrical Engineering and Computer Science, MIT, 1995.
  • B.S. in Computer Science and Engineering, MIT, 1995.