HPCToolkit
events.c
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46 
47 /* -*-C-*- */
48 
49 /****************************************************************************
50 //
51 // File:
52 // events.c
53 //
54 // Purpose:
55 // Supported events for profiling.
56 //
57 // Description:
58 // [The set of functions, macros, etc. defined in the file]
59 //
60 // Author:
61 // Written by John Mellor-Crummey and Nathan Tallent, Rice University.
62 //
63 // Adapted from parts of The Visual Profiler by Curtis L. Janssen
64 // (events.c).
65 //
66 *****************************************************************************/
67 
68 #include <string.h>
69 #include <stdio.h>
70 
71 #include <papiStdEventDefs.h>
72 #include <papi.h>
73 
74 #include "hpcrun_events.h"
75 
76 papi_event_t hpcrun_event_table[] = {
77 { PAPI_L1_DCM, "PAPI_L1_DCM", "Level 1 data cache misses" },
78 { PAPI_L1_ICM, "PAPI_L1_ICM", "Level 1 instruction cache misses" },
79 { PAPI_L2_DCM, "PAPI_L2_DCM", "Level 2 data cache misses" },
80 { PAPI_L2_ICM, "PAPI_L2_ICM", "Level 2 instruction cache misses" },
81 { PAPI_L3_DCM, "PAPI_L3_DCM", "Level 3 data cache misses" },
82 { PAPI_L3_ICM, "PAPI_L3_ICM", "Level 3 instruction cache misses" },
83 { PAPI_L1_TCM, "PAPI_L1_TCM", "Level 1 total cache misses" },
84 { PAPI_L2_TCM, "PAPI_L2_TCM", "Level 2 total cache misses" },
85 { PAPI_L3_TCM, "PAPI_L3_TCM", "Level 3 total cache misses" },
86 { PAPI_CA_SNP, "PAPI_CA_SNP", "Snoops" },
87 { PAPI_CA_SHR, "PAPI_CA_SHR", "Request access to shared cache line (SMP)" },
88 { PAPI_CA_CLN, "PAPI_CA_CLN", "Request access to clean cache line (SMP)" },
89 { PAPI_CA_INV, "PAPI_CA_INV", "Cache Line Invalidation (SMP)" },
90 { PAPI_CA_ITV, "PAPI_CA_ITV", "Cache Line Intervention (SMP)" },
91 { PAPI_L3_LDM, "PAPI_L3_LDM", "Level 3 load misses " },
92 { PAPI_L3_STM, "PAPI_L3_STM", "Level 3 store misses " },
93 { PAPI_BRU_IDL, "PAPI_BRU_IDL", "Cycles branch units are idle" },
94 { PAPI_FXU_IDL, "PAPI_FXU_IDL", "Cycles integer units are idle" },
95 { PAPI_FPU_IDL, "PAPI_FPU_IDL", "Cycles floating point units are idle" },
96 { PAPI_LSU_IDL, "PAPI_LSU_IDL", "Cycles load/store units are idle" },
97 { PAPI_TLB_DM, "PAPI_TLB_DM", "Data translation lookaside buffer misses" },
98 { PAPI_TLB_IM, "PAPI_TLB_IM", "Instr translation lookaside buffer misses" },
99 { PAPI_TLB_TL, "PAPI_TLB_TL", "Total translation lookaside buffer misses" },
100 { PAPI_L1_LDM, "PAPI_L1_LDM", "Level 1 load misses " },
101 { PAPI_L1_STM, "PAPI_L1_STM", "Level 1 store misses " },
102 { PAPI_L2_LDM, "PAPI_L2_LDM", "Level 2 load misses " },
103 { PAPI_L2_STM, "PAPI_L2_STM", "Level 2 store misses " },
104 { PAPI_L1_DCH, "PAPI_L1_DCH", "Level 1 D cache hits" },
105 { PAPI_L2_DCH, "PAPI_L2_DCH", "Level 2 D cache hits" },
106 { PAPI_L3_DCH, "PAPI_L3_DCH", "Level 3 D cache hits" },
107 { PAPI_TLB_SD, "PAPI_TLB_SD", "TLB shootdowns" },
108 { PAPI_CSR_FAL, "PAPI_CSR_FAL", "Failed store conditional instructions" },
109 { PAPI_CSR_SUC, "PAPI_CSR_SUC", "Successful store conditional instructions" },
110 { PAPI_CSR_TOT, "PAPI_CSR_TOT", "Total store conditional instructions" },
111 { PAPI_MEM_SCY, "PAPI_MEM_SCY", "Cycles Stalled Waiting for Memory Access" },
112 { PAPI_MEM_RCY, "PAPI_MEM_RCY", "Cycles Stalled Waiting for Memory Read" },
113 { PAPI_MEM_WCY, "PAPI_MEM_WCY", "Cycles Stalled Waiting for Memory Write" },
114 { PAPI_STL_ICY, "PAPI_STL_ICY", "Cycles with No Instruction Issue" },
115 { PAPI_FUL_ICY, "PAPI_FUL_ICY", "Cycles with Maximum Instruction Issue" },
116 { PAPI_STL_CCY, "PAPI_STL_CCY", "Cycles with No Instruction Completion" },
117 { PAPI_FUL_CCY, "PAPI_FUL_CCY", "Cycles with Maximum Instruction Completion" },
118 { PAPI_HW_INT, "PAPI_HW_INT", "Hardware interrupts " },
119 { PAPI_BR_UCN, "PAPI_BR_UCN", "Unconditional branch instructions executed" },
120 { PAPI_BR_CN, "PAPI_BR_CN", "Conditional branch instructions executed" },
121 { PAPI_BR_TKN, "PAPI_BR_TKN", "Conditional branch instructions taken" },
122 { PAPI_BR_NTK, "PAPI_BR_NTK", "Conditional branch instructions not taken" },
123 { PAPI_BR_MSP, "PAPI_BR_MSP", "Conditional branch instructions mispred" },
124 { PAPI_BR_PRC, "PAPI_BR_PRC", "Conditional branch instructions corr. pred" },
125 { PAPI_FMA_INS, "PAPI_FMA_INS", "FMA instructions completed" },
126 { PAPI_TOT_IIS, "PAPI_TOT_IIS", "Total instructions issued" },
127 { PAPI_TOT_INS, "PAPI_TOT_INS", "Total instructions executed" },
128 { PAPI_INT_INS, "PAPI_INT_INS", "Integer instructions executed" },
129 { PAPI_FP_INS, "PAPI_FP_INS", "Floating point instructions executed" },
130 { PAPI_LD_INS, "PAPI_LD_INS", "Load instructions executed" },
131 { PAPI_SR_INS, "PAPI_SR_INS", "Store instructions executed" },
132 { PAPI_BR_INS, "PAPI_BR_INS", "Total branch instructions executed" },
133 { PAPI_VEC_INS, "PAPI_VEC_INS", "Vector/SIMD instructions executed" },
134 { PAPI_FLOPS, "PAPI_FLOPS", "Floating Point instructions per second" },
135 { PAPI_RES_STL, "PAPI_RES_STL", "Any resource stalls" },
136 { PAPI_FP_STAL, "PAPI_FP_STAL", "FP units are stalled " },
137 { PAPI_TOT_CYC, "PAPI_TOT_CYC", "Total cycles" },
138 { PAPI_IPS, "PAPI_IPS", "Instructions executed per second" },
139 { PAPI_LST_INS, "PAPI_LST_INS", "Total load/store inst. executed" },
140 { PAPI_SYC_INS, "PAPI_SYC_INS", "Synchronization instructions executed" },
141 
142 #if 0 /* Begin Rice I2 additions (FIXME) */
143 { ITA2_BACK_END_BUBBLE_ALL, "ITA2_BACK_END_BUBBLE_ALL", "<fixme>" },
144 #endif /* End Rice I2 additions */
145 
146 { -1, NULL, "Invalid event type" }
147 };
148 
149 /****************************************************************************/
150 
151 const papi_event_t *
152 hpcrun_event_by_name(const char *name)
153 {
154  papi_event_t *i = hpcrun_event_table;
155  for (; i->name != NULL; i++) {
156  if (strcmp(name, i->name) == 0) return i;
157  }
158  return NULL;
159 }
160 
161 const papi_event_t *
163 {
164  papi_event_t *i = hpcrun_event_table;
165  for (; i->name != NULL; i++) {
166  if (i->code == code) return i;
167  }
168  return NULL;
169 }
170 
171 /****************************************************************************/
172 
173 /*
174  * output an indented comma-separated list with lines wrapped around
175  * 70 characters
176  */
177 void
178 hpcrun_write_wrapped_event_list(FILE* fs, const papi_event_t* e)
179 {
180  /* initial values */
181  static char *sep = " ";
182  static int linelen = 0;
183 
184  if (!e) { return; }
185 
186  /* Prospective line length (see format string below) */
187  linelen += strlen(sep);
188  linelen += strlen(e->name);
189 
190  /* If the prospective line is beyond our line limit, wrap and try
191  again. We are guaranteed that the event name is not longer than
192  our line limit (causing an infinite loop).
193  */
194  if (linelen > 70) {
195  fputs("\n", fs);
196  sep = " ";
197  linelen = 0;
199  return;
200  }
201 
202  fprintf(fs, "%s%s", sep, e->name);
203 
204  sep = ", "; /* default separator to continue next line */
205 }
206 
207 /*
208  Write the event and its description to stream 'fs'
209 */
210 void
211 hpcrun_write_event(FILE* fs, const papi_event_t* e)
212 {
213  if (!e) { return; }
214 
215  fprintf(fs, " %s - %s\n", e->name, e->description);
216 }
const papi_event_t * hpcrun_event_by_code(int code)
Definition: events.c:162
void hpcrun_write_event(FILE *fs, const papi_event_t *e)
Definition: events.c:211
papi_event_t hpcrun_event_table[]
Definition: events.c:76
const papi_event_t * hpcrun_event_by_name(const char *name)
Definition: events.c:152
void hpcrun_write_wrapped_event_list(FILE *fs, const papi_event_t *e)
Definition: events.c:178
#define NULL
Definition: ElfHelper.cpp:85